SPACE CHIPS: PURPOSE, DESIGNING, FABRICATION AND FRONTIER TECHNOLOGY
Conference on Purpose, Design, Fabrication and Frontier Technologies in Space-Grade Microelectronics
Date: 16 October 2026
Venue: MERI Group of Institutions, New Delhi Campus
Organized by: MERI Department of Space Studies (MERI DSS) and SIA-India
About the Conference
The global space sector is shifting towards miniaturized, intelligent, and resilient hardware for extreme orbital and deep-space environments. At the core are Space Chips specialized microelectronics, ICs, SoCs, and FPGAs that power satellites, launch vehicles, probes, and orbital constellations. Unlike terrestrial chips, space-grade semiconductors must withstand radiation, cosmic rays, thermal extremes, vacuum, and launch stresses. With the rise of autonomous satellites, optical communications, and AI-based payloads, missions require lowSWaP-C silicon, Radiation-Hardened-by-Design (RHBD) techniques, wide-bandgap materials, and advanced packaging.
The conference “Space Chips: Purpose, Designing, Fabrication, and Frontier Technology” brings together experts to discuss the design, fabrication, packaging, testing, and strategic importance of next-generation space microelectronics. As missions increasingly require realtime edge processing for hyperspectral imaging, SAR, navigation, and optical links, space chips face challenges related to radiation, thermal cycling, mature-node limitations, and supply-chain restrictions.
These challenges highlight the need for an end-to-end pipeline covering space chip design, fabrication, packaging, testing, and qualification, making reliable and sovereign space-grade microelectronics strategically important for India.
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Event Schedule
Our Speakers
Prof Lalit Aggarwal
Vice President,
MERI Group of Institutions
Lt Gen PJS Pannu (Retd.)
PVSM, AVSM, VSM, PhD
Chief Mentor & Dean,
Department of Space Studies,
MERI Group of Institutions
V Adm AB Singh (Retd.)
PVSM, AVSM, VSM
Former Flag Officer Commanding - in - Chief
WNC, ENC
Shri Satheesh Shenoi
MoES Chair Professor/Scientist,
Former Director INCOIS
V Adm Adhir Arora
AVSM, NM
Former Chief Hydrographer to the Government of India
Shri Mustafa Elmoslhey
Founder and CEO,
Seker Space Intelligence S.A.,
Luxembourg
R Adm Dalbir S Gujral
NM (Retd.)
Cdr. P. K. Srivastava
Scientist 'G',
Ministry of Earth Sciences
Capt. PMS Lamba
Ex - Merchant Navy
Dr. Rishi Sharma
Senior Fisheries Resources Officer at FAO,
Rome, Italy
Who Should Attend
- Semiconductor design engineers and VLSI architects
- Space microelectronics researchers and physicists
- Foundry, ATMP, and OSAT industry professionals
- ISRO, DRDO, and DAE scientists and systems engineers
- Defense microelectronics experts and armed forces representatives
- Fabless semiconductor startups and space-tech innovators
- Academicians and scholars in microelectronics and aerospace engineering
- Representatives from MeitY, ISM, IN-SPACe, and NITI Aayog policy divisions
Scope of the Conference
The conference will provide a comprehensive interdisciplinary platform for discussing emerging advancements, operational challenges, and future opportunities in space semiconductors and microelectronics engineering. The scope covers the end-to-end ecosystem of space chips, from specialized instruction set architectures (ISAs) and radiation-hardened design methodologies to advanced fabrication, packaging, reliability testing, and sovereign supply chains.
Space Chip Architecture and Design
The conference will explore the architecture and micro-architectural design of space-grade SoCs, FPGAs, and ASICs, including space- grade open-source RISC-V architectures and custom ISA extensions.
Radiation-Hardened Technologies
Discussions will cover Radiation-Hardened-by-Design (RHBD) and Radiation-Hardened-byProcess (RHBP) strategies, Total Ionizing Dose (TID) and Single Event Effects (SEE) mitigation mechanisms, fault-tolerant computing architectures, Triple Modular Redundancy (TMR), selfhealing circuits, and memory error correction codes (ECC).
Semiconductor Materials and Fabrication
The scope will examine advanced semiconductor fabrication nodes and mature heritage nodes for space applications, including CMOS, Silicon-on-Insulator (SOI), Silicon-Germanium (SiGe), and Wide-Bandgap GaN/SiC technologies.
Advanced Packaging and Chiplets
The conference will address heterogeneous integration, Chiplet architectures, 2.5D/3D System -in-Package (SiP), interposers, and ATMP/OSAT processes for high-reliability space applications.
AI, Edge Computing and Processors
Sessions will explore on-board AI/ML edge-compute accelerators, Neural Processing Units (NPUs), radiation-tolerant processors, RISC-V space cores, SoCs for payload processing, and real-time computer vision.
MEMS, Sensors and Photonic Technologies
The scope includes MEMS sensors, micro-actuators, atomic clocks, space-qualified inertial measurement units (IMUs), RF MEMS, Silicon Photonics, and high-speed optical interconnects for space computing.
Hardware Security and
Space Qualification
Discussions will include hardware Trojan prevention, Physical Unclonable Functions (PUFs), cryptographic coprocessors, space qualification standards, testing, screening, and testbeds.
Low-Power and Thermal-Aware
Design
The conference will explore ultra-low-power thermal-aware chip design and energyharvesting management units for space applications.
Small Satellite and Commercial Electronics
The scope will cover CubeSat, SmallSat, and high-density commercial off-the-shelf (COTS) screen-based microelectronics.
Testing, Qualification and Packaging Ecosystem
The conference will address testing and qualification requirements, including MIL-STD-883 and ESCC, as well as Foundries, Assembly, Testing, and Packaging (ATMP/OSAT) for highreliability electronics.
Defense, Sovereignty and
Collaboration
The discussions will cover defense-oriented dual-use microelectronics, sovereign hardware security, and industry–academia–foundry collaboration in semiconductor R&D.
Frontier Technologies
Emerging deep-tech innovations including neuromorphic chips, 2D materials, and quantum processing units for space will also form part of the conference scope.
Objectives of the Conference
Examine Space Semiconductor Challenges
To examine the material, architectural, and physics-of-failure challenges associated with operating semiconductors in harsh space radiation and thermal environments.
Advance Radiation-Hardened Design
To discuss advancements in Radiation-Hardened-by-Design (RHBD) libraries, fault-tolerant logic, and radiation-tolerant processor architectures.
Explore Emerging Semiconductor Technologies
To explore emerging technologies including space-grade RISC-V processors, GaN-based RF power amplifiers, Chiplets, and on-board AI accelerators.
Evaluate Packaging and Qualification
To evaluate modern packaging, assembly, and qualification methodologies, including 3D SiP, OSAT, and screening standards, for space microelectronics.
Align Domestic Manufacturing with Space Requirements
To align domestic semiconductor manufacturing initiatives, including SCL Mohali, new commercial fabs, and ATMP units, with the strategic requirements of the Indian space sector.
Foster Interdisciplinary Collaboration
To foster collaboration between fabless startups, academic researchers, defense labs, foundries, and space agencies.
Accelerate Sovereign Space-Grade Silicon
To formulate policy and technological recommendations to accelerate India’s journey towards sovereign space-grade silicon manufacturing under Viksit Bharat @2047.
Global Space Chip Development and India’s Path to Silicon Sovereignty
Leading spacefaring nations are heavily investing in custom space silicon, advanced packaging, and sovereign semiconductor fabs to maintain technological capabilities and independence.
United States
The United States focuses on rad-hard high-performance edge computing, RISC-V space processors, GaN RF MMICs, and the DoD SHIELD program. Advancements include flightproven rad-hard multi-core processors, the DoD Microelectronics Commons, advanced 3D packaging for small satellite constellations, and space-qualified AI accelerators.
European Union / ESA
The European Union and ESA focus on sovereign space processors, the DAHLIA project, rad-tolerant ARM/RISC-V architectures, and the European Processor Initiative (EPI). Developments include open-source RISC-V rad-hard SoCs, high-reliability STMicroelectronics space-qualified portfolios, and standardized European space-chip testing protocols.
China
China focuses on autonomous space chipsets, high-density spatial AI accelerators, and indigenous rad-hard fabs. Its developments include near-complete supply-chain independence for space-grade microelectronics, custom space chips for large LEO constellations, and deep-space processing units.
Japan
Japan focuses on rad-hard SOI technology, high-precision MEMS sensors, GaN-on-SiC power devices, and space-grade chip packaging. Developments include JAXA-qualified ultra-low-power SOI microprocessors, high-frequency satellite communication chips, and advanced MEMS gyroscopes for deep-space probes.
India
India is focusing on indigenous space processors, including the SCL Mohali Vikram series and IIT-M SHAKTI variants, and India Semiconductor Mission (ISM) space initiatives. Developments include silicon-proven 180nm space-grade ASICs/SoCs at SCL Mohali, the emergence of private fabless startups, and the national push for domestic OSAT and compound semiconductor fabs.
Venue
MERI Group of Institutions, Janakpuri, New Delhi
Organized by: MERI Department of Space Studies